FIFO (electronic)

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In digital electronics, a FIFO (acronym for first-in, first-out) is a digital circuit that stores incoming data in internal memory and outputs the stored data in the order it was received. The oldest stored data is typically output with little or no delay. This is in contrast to a shift register, which requires data to sequentially propagate through memory before it is output. FIFOs are commonly used for buffering and flow control between hardware devices or between software and hardware devices which, over finite intervals, operate at different data rates.

A FIFO primarily consists of a pair of counters that serve as read and write memory address registers, an addressable memory array, and status and control logic. The memory typically is dual-ported to allow concurrent FIFO read and write operations, and consists of a register file or dual-ported RAM (random access memory). Although is is not required, the memory storage capacity (in words) is usually a power of two, as this tends to simplify circuitry and improve speed performance. The data written to and read from a FIFO typically have a fixed word size (number of bits) equal to that of the internal memory.

A FIFO is implemented as a circular buffer that employs two memory address registers (MARs) to store the addresses of (pointers to) the next memory locations to be accessed:

• Read MAR (RMAR) - contains next location to read data from
• Write MAR (WMAR) - contains next location to write data to

Each MAR is implemented as a counter, with the count incremented every time data is transferred (WMAR incremented upon FIFO write; RMAR incremented upon FIFO read).^[1] Initially both MARs point to the first memory location and the FIFO is empty. A FIFO becomes full when the write address reaches the read address, and empty when the read address reaches the write address. Consequently, upon FIFO becoming full or empty, the read and write memory addresses are equal, and thus ambiguous if used to monitor the FIFO level (number of words stored).

In many FIFOs, to distinguish between empty and full, each MAR has an additional bit beyond what is needed to address memory. All MAR output bits except the most significant bit (MSB) (i.e., the LSBs) serve as the memory address. Conversely, all output bits, including the MSB, are used to monitor the FIFO level.

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In cases where the MARs employ binary counters, the current FIFO level (number of words stored) is the difference between their binary output values: ${\displaystyle level=WMAR-RMAR}$. For other output encodings (e.g., Gray code), the MAR outputs must be converted to binary before computing the difference. In either case, the following hold true:

• The FIFO is empty when RMAR and WMAR are equal
• The FIFO is full when RMAR and WMAR differ only in their MSBs

A FIFO typically outputs status signals that indicate whether particular data level thresholds are met. Common examples of such status flags include full, empty, half full, almost full, and almost empty.

A synchronous FIFO is an electronic FIFO that uses a common clock for reading and writing. Because read and write operations take place in the same clock domain, flags may be generated via either pointer arithmetic or by using a dedicated counter to monitor the FIFO level.

An asynchronous FIFO is an electronic FIFO that uses different clocks for reading and writing. To avoid errors due to metastability, asynchronous FIFOs typically use Gray code for the read and write pointers, and flags are generated via pointer arithmetic.

• Leaky bucket approach
• Ring buffer